1) Field of the Invention
The present invention relates to a transmission signal correction circuit.
2) Description of the Related Art
There has been a rapid increase in operation frequencies of large scale integrations (LSI). This has been made possible by increasing the speed of signal transmission between LSIs.
Some of the LSIs employ a parallel transmission scheme when performing transmission between LSIs. In such LSIs, since there is less space for interconnect on a system board, skew is produced between bits so that the operation frequency can not be increased much. One approach to solve this problem is to reduce the number of parallel signal lines and, on the other hand, increase the transfer rate per bit. This approach makes it possible to largely increase data transfer rate of each bit. However, there is a drawback in this approach that an input waveform becomes dependent on a data series called inter symbol interference (ISI) on its reception side and causes degradation in signal quality. Means and measures that can take care of this drawback are being researched.
The ISI are explained below with reference to FIG. 20 to FIG. 23. FIG. 20 is a conceptual diagram for explaining attenuation characteristics of substrate interconnect. FIG. 21 is a conceptual diagram of digital signal waveforms that are transmitted through the substrate interconnect. FIG. 22 is a conceptual diagram of reduced eye patterns due to the ISI. FIG. 23 is a conceptual diagram of effects obtained when waveforms are controlled on their transmission side.
As shown in FIG. 20, the signal loss becomes enormous on a system board during high-speed data transmission exceeding 1 gigahertz (GHz). As a result, when a data series is an alternate pattern between high (H) level and low (L) level, amplitudes and times are aligned as shown with (a) in FIG. 21. However, when a bit pattern is, for example, “HLLHLH”, the amplitude of the signal at “H” after “LL” may lower by a certain level 121 caused by the ISI, and the transmission time may delay by a certain time 122 as shown with (b) in FIG. 21.
Specifically, FIG. 22 depicts eye patterns obtained by overwriting the waveforms of FIG. 21 within one period. Amplitude 125 attenuates, and significant data time 126 reduces, which causes an opening of an eye to be made smaller and data identification to be difficult on its reception side. To suppress degradation in signal quality due to ISI, a method of controlling waveforms on the transmission side can be employed. According to this method, as shown in FIG. 23, by improving output amplitude 131 so as to increase reception amplitude, significant data period 132 is also improved.
Conventional devices for controlling waveforms are shown in FIG. 24 and FIG. 25. FIG. 24 is a circuit diagram of a simplified pre-emphasis circuit disclosed in Japanese Patent Application Laid Open (JP-A) No. 2002-368600 (see [0009] to [0013], FIG. 1 and FIG. 2). In this circuit, source electrodes of a differential pair of transistors 141 and 142 to which differential signals (input 1, input 2) are input are connected to power sources Vdd through respective loads 143 and 144. Commonly connected drain electrodes thereof are connected to a low potential power source Vss through a current source 145. Differential outputs (output 1, output 2) are output from nodes between the source electrodes of the differential pair of transistors 141 and 142 and the loads 143 and 144, respectively.
A circuit for the outputs includes a serial circuit of a switch 146 and a current source 147 provided in parallel with the current source 145, and an edge detector 148 that on-off controls the switch 146. The edge detector 148 includes a delay circuit that adds a delay operation to the input signal 1 as one of the differential input signals, and an exclusive OR (XOR) circuit that logically XORs the input signal 1 with the output of the delay circuit and provides a switch control signal to the switch 146.
When polarities of the output data are switched, the edge detector 148 asynchronously generates narrow pulse signals with a pulse width determined by a delay value of the delay circuit. The switch 146 connects the current source 147 to the drain electrodes commonly connected to the differential pair of transistors 141 and 142 during a period when the edge detector 148 outputs pulse signals to allow a drive current to increase. Consequently, the current of the output circuit increases, so that the output amplitude increases. This makes it possible to correct the waveform on the reception side.
FIG. 25 is a block diagram of a simplified driver circuit for signal transmission disclosed in JP-A No. H11-345054 (see [0009], FIG. 2). The driver circuit includes a pre-circuit 151 that is an amplitude-variable type, and a data string detector 153 that can change output amplitude of the pre-circuit 151 according to a data string of input signals. The driver circuit also includes a final-stage output circuit 152 that amplifies the thus changed output amplitude of the pre-circuit 151 and outputs it, and the waveform is thereby corrected. A control function is defined as essential or recommended option in signal specification such as “PCI-Express™ base specification revision 1.0” and “InfiniBand™ Architecture specification volume 2 revision 1.0a”.
In addition, as a method of controlling waveforms in a complementary metal oxide semiconductor (CMOS) circuit, U.S. Pat. No. 6,518,792B2 (see FIG. 6A) discloses a method of operating a CMOS output circuit for correction according to an input data string. The CMOS output circuit for correction is arranged in parallel with a CMOS output-circuit usually used, and a pre-emphasis circuit is provided in the input stage of both the CMOS circuits.
The method disclosed in JP-A No. 2002-368600 is designed for a current mode logic (CML) circuit and temporarily changes characteristics of a constant current source. However, this causes the quality of a differential output signal to degrade. Moreover, if an edge detector that detects a high-frequency component is used as a circuit that detects a data string to be corrected, effects due to correction are determined depending on a delay value in a delay circuit used in the edge detector. Therefore, a high-frequency component detected may fluctuate in response to a change in a delay value due to fluctuations in circuit features, which causes the effects due to correction to fluctuate. Furthermore, the method disclosed in JP-A No. 2002-368600 cannot be used in the CMOS circuit.
In the method disclosed in JP-A No. H11-345054, the CMOS circuit is used, but an intermediate voltage value is used to cause a through current to increase and current consumption to increase. Since the intermediate voltage is weak in noise, the operation of the circuit becomes unstable to noise. The data string detector controls output amplitude of the pre-circuit-in an analog manner by a method of mixing signals using the delay circuit, but the effects due to correction fluctuate when the delay value of the delay circuit changes as explained above. Furthermore, the method disclosed in JP-A No. H11-345054 cannot be used in the CML that handles differential signals. In the method disclosed in U.S. Pat. No. 6,518,792B2, the configuration of the pre-emphasis circuit is complicated.
As the data string detector, there is an example in which static random access memory (SRAM) is used as a decoder when a data string to be corrected consists of 4 bits, but this example requires writing to the SRAM each time the power source is turned on or off. Moreover, in the methods disclosed in JP-A No. 2002-368600 and JP-A No. H11-345054, the improvement in the amplitude is the prime purpose, and the improvement in the delay time is secondarily performed, which is inadequate control for the waveforms. Particularly, in the method of correcting waveforms and input amplitudes with respect to analog outputs, performance of clock data recovery (CDR) on the reception side may cause an increase in jitter of a recovered clock.